2312683 – Design digitaler Schaltkreise

The following topics will be covered in the lectures: circuit design using the hardware description language Verilog; combinational and sequential CMOS digital circuits; digital transmitter/receiver (transceiver), oscillators, PLLs, volatile and non-volatile integrated memory cells. In the exercises, digital design will be carried out using Cadence software tools. Circuits will be designed and simulated using Verilog. A netlist will be generated with a synthesis tool, and the chip layout will be created using a place & route tool. Lectures will be held both in person and via Zoom. Slides and lecture notes will be uploaded. If you have any questions regarding the lectures or exercises, please contact ivan.peric@kit.edu and richard.leys@kit.edu.