[Online Seminar] The trend of increasing the number of integrated cores on a single chip has become apparent in chip manufacture. Some commercial industrial examples are 48-core Intel’s SCC, 61-core Intel Xeon Phi, and Tilera’s processor family. To exploit available multi cores on the chip, multi-threaded applications have emerged to run multiple threads of each application in parallel on the available cores. In order to optimize for performance in multicore chips, a resource management technique is required to distribute the chip’s resources among the different applications; i.e., determine the number of cores that should be allocated to each application and the voltage and frequency levels of these cores. Moreover, to be efficient, a resource management technique needs to consider the implications of its decisions on the physical state of the cores like the temperature and the power consumption. In this seminar, students will review cutting-edge state-of-the-art research (publications) in the area of resource management for multicores. The findings will be summarized in a seminar report and presented to CES members and to the other members of the course. Students are welcome to suggest own topics related to multicores, but this is not required.