Wartungsankündigung: Wichtig: bitte beachten Sie unsere Wartungsankündigungen für Dienstag, den 02. April 2024 und Freitag, den 05. April 2024 auf der Magazineinstiegseite!
Maintenance announcement: please note our maintenance announcements for Tuesday, 02 April 2024 and Friday, 05 April on the repository page!
Wartungshinweis: wegen wichtigen Wartungsarbeiten an den OpenCast-Servern, bitten wir Sie über das Osterwochenende keine neuen Videos hochzuladen! Die bereits vorhandenen OpenCast-Videos stehen aber wieder zur Verfügung.
Symbol Kurs

2424302 – Customized Embedded Processor Design

The student will be supervised to learn how to adapt and customise a processor. This is done using state-of-the-art tool chains that can generate the required hardware description of the processor based on the optimisation and customisation that the student wants to do such as targeting performance and/or power goals. In addition, synthesis and implementation of the generated processor will be also done at the end using an FPGA platform. Due to prevailing conditions, this lab is available ONLINE, and regular meetings/discussions will be carried out on Zoom.

Allgemeine Informationen

Wichtige Informationen
At the beginning of the semester there would a Kick-off meeting with a mutual agreement. Then weekly meeting are carried accordingly.

Kick-off happen during starting weeks of semester. Please join us on Monday 12th April 16:00 (or tell me your availability). (click on Zoom link for joining Kick-off).
Kursprogramm
an kick off meeting
8 weekly sessions
a presentation at the end of the semester
Dateien zum Herunterladen
Kick-Off Introductory Presentation (Dateigröße : 16721486 Bytes)

Veranstaltungsdaten

Dozent(en)
12
Abschluß
Diplom & Bachelor & Master
SWS
4
Credits
4
Start
15. Aug 2021
Ende
30. Mär 2022
Veranstaltungsart
Praktikum
Ort
Online/CES-ITEC
Termin
2-3 hours once in a week, mutually decided
Zyklus
wöchtl.

Zusammenfassung

The student will be supervised to learn how to adapt and customise a processor. This is done using state-of-the-art tool chains that can generate the required hardware description of the processor based on the optimisation and customisation that the student wants to do such as targeting performance and/or power goals. In addition, synthesis and implementation of the generated processor will be also done at the end using an FPGA platform.
Due to prevailing conditions, this lab is available ONLINE, and regular meetings/discussions will be carried out on Zoom.

Allgemein

Sprache
Deutsch
Copyright
This work has all rights reserved by the owner.

Verfügbarkeit

Zugriff
Unbegrenzt – wenn online geschaltet
Aufnahmeverfahren
Sie können diesem Kurs direkt beitreten.
Zeitraum für Beitritte
Bis: 30. Okt 2021, 00:00
Veranstaltungszeitraum
18. Okt 2021 - 30. Mär 2022

Für Kursadministratoren freigegebene Daten

Daten des Persönlichen Profils
Benutzername
Vorname
Nachname
E-Mail
Matrikelnummer

Zusätzliche Informationen

Objekt-ID
2158793
Link zu dieser Seite